The present application relates to a semiconductor integrated circuit device (or semiconductor device), and is applicable to, for example, a semiconductor integrated circuit device having an analog circuit area and a digital circuit area.
Japanese Unexamined Patent Publication Laid-Open No. 2001-267491 (Patent Document 1) or U.S. Patent Application Publication No. 2002-24125 (Patent Document 2) corresponding to it relates to a multichip package in which a plurality of semiconductor chips are arranged side by side at the surface of a semiconductor chip and flip-chip bonded. There has been disclosed therein a technology in which the semiconductor chips to be flip-chip bonded are die-bonded in thin order in such a manner that a flip-chip bonding collet and the previously-bonded chips do not interfere with each other.
Japanese Unexamined Patent Publication Laid-Open No. 2008-251731 (Patent Document 3) or U.S. Pat. No. 8,018,048 (Patent Document 4) corresponding to it relates to a resin-sealed multichip package in which a plurality of semiconductor chips are arranged side by side and die-bonded. There has been disclosed therein a technology in which the semiconductor chip largest in thickness is mounted to the central part of the package to prevent the package from being curved.
Japanese Unexamined Patent Publication Laid-Open No. 2004-356382 (Patent Document 5) relates to a resin-sealed multichip package in which a plurality of semiconductor chips are arranged side by side over a lead frame and die-bonded and the chips are interconnected therebetween by bonding wires. There has been disclosed therein a technology in which in order to prevent a wire shift or the like, the semiconductor chips thick in thickness are coupled to each other by ball bonding, and the semiconductor chips thin in thickness are coupled to each other by wedge bonding.
Japanese Unexamined Patent Publication Laid-Open No. 2012-169417 (Patent Document 6) relates to a high-frequency resin-sealed multichip package in which a plurality of semiconductor chips are arranged side by sided and die-bonded using a lead frame, and the chips are interconnected therebetween by bonding wires. There has been disclosed therein a technology in which the semiconductor chip on the high-frequency side is made thicker in thickness than other semiconductor chips to ensure mechanical strength.
Japanese Unexamined Patent Publication Laid-Open No. Hei 9 (1997)-223705 (Patent Document 7) relates to a resin-sealed package in which semiconductor chips each having an analog circuit area and a digital circuit area are mounted overt die pads. There has been disclosed therein a technology in which the die pads below the analog circuit area and the die pads below the digital circuit area are separated from one another.
International Patent Publication No. 2003/3461, Pamphlet (Patent Document 8) relates to the layout or the like of semiconductor chips each having an analog circuit area and a digital circuit area. There has been disclosed therein a technology in which they are separated from one another by a well structure, a guard ring and the like to prevent noise from propagating from the digital circuit area to the analog circuit area.